The present invention relates to semiconductor devices, and more specifically, to using a sacrificial silicon germanium channel in fabricating transistors.
In building transistors, the replacement gate process architecture avoids the problems of work function material stability seen in the gate first architecture. However, the replacement gate architecture requires the insertion of new process modules into the flow, such as chemical mechanical polishing/planarization (CMP). The process is to form a dummy gate structure used to self-align the source and drain implant and anneals. The dummy gate materials are then stripped and replaced with the high-κ and metal gate materials. The flow forms an SiO2 or SiON interface between the silicon substrate and the high-k dielectric. A thin layer of metal is then deposited above the high-k dielectric to set the work function, followed by deposition of low resistivity metal in the gate trench. This is followed by forming the source and drain, salicidation, and depositing the contact etch stop and first inter-layer dielectric. There are other variants of the deposition sequence as well.